1. Field of the Invention
This invention relates to the semiconductor memory devices, and more specifically to semiconductor memory devices that are easy to fabricate while compatible with conventional dynamic random access memories (DRAMS).
2. Description of the Related Art
A conventional DRAM cell 100 is illustrated schematically in FIG. 1. It consists of one access transistor 102 and one storage capacitor 104. A gate 106 of the transistor 102 controls the switching of the transistor 102, which allows or prohibits the movement of charges between the capacitor 104 and a bit line 108. While one plate of the capacitor 104 is coupled to the access transistor 102, the other plate is coupled to a common line 109. The data stored in cell 100 (i.e., digital data “0” or “1”) is determined by sensing the amount of charges stored in capacitor 104.
In order to provide enough signal margins for sensing, it is necessary to have a large capacitor with a large capacitance. On the other hand, it is desirable to reduce the size of a cell. As a result, exotic capacitor structures (e.g., trench and stack) that have large surface areas have been developed. These structures are fabricated using complicated processes, which increase costs and reduce yield.
Many people have realized the problem and attempted to build DRAM cells without using complicated capacitor fabrication processes. One example is the so-called “floating body cell” (FBC), shown as a cell 130 in cross-section in FIG. 2. The cell 130 consists of a transistor that has a gate 132 and a gate oxide film on top of a body 134. Two impurity regions 136 and 138 straddle the body 134. The transistor is fabricated on top of an insulator 140, which is disposed on top of a substrate 142. Instead of storing charges in a capacitor as in capacitor-based DRAM cells, this device stores charges in the body 134 of the transistor. The charges can reduce the threshold voltage of the transistor, thereby increasing current flow in a read operation. By sensing the transistor current level, the amount of charge in the body 134 can be determined. A variation of the FBC is the so-called twin-transistor random access memory. This device has two transistors: one for switching and the other for storing a charge. This two-transistor arrangement provides more reliable cell operation because the switching transistor prevents a disturbing event from affecting the bit line.
Although these types of cells are easier to fabricate than conventional DRAM cells, there are many problems. First, the difference in current between data “1” state and data “0” state is very small, and it is difficult to read the difference. Second, the control signals are very complicated: many different voltage levels with complex timing requirements are needed for read and write operations. Also, current sensing is used instead of voltage sensing in conventional DRAM. Current sensing is not compatible with conventional DRAM circuitry. Third, data disturbance is a very serious problem, especially for a single transistor type cell arrangement. Data disturbance is typically the result of leakage currents transiting the junctions of, for example, the impurity regions 136 and 138 depicted in FIG. 2. These leakage currents can inadvertently change the logic state sensed during a read operation, resulting in erroneous data.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.